Processes of making integrated circuit structures have line widths of microscopic dimensions currently measured in nanometers (nm). Process generations having different size line widths from each other, and thought of in general, are called process nodes. An integrated circuit or “chip” generally has a semiconductor substrate (e.g. silicon Si, silicon germanium SiGe, or gallium arsenide GaAs, or other substance), or instead may have an insulating layer, on which semiconductor devices like transistors and diodes are fabricated in a semiconductor on insulator (SOI) technology. Over the semiconductor devices, alternating layers of insulator and conductor are provided, like a layer cake on a cake pan. The conductor layers are patterned and etched into microscopic conducting lines. The conducting lines are used to interconnect the semiconductor devices to make integrated circuits of varying complexity that under a microscope look like a grid of streets, except at many levels. The conductor layers often are metal but any electrical conductive substance can be useful. One example is polysilicon (poly), which is doped and made conductive for making transistor gates and can also form interconnect lines to the gates. Metal layers for wires are often provided above the poly interconnect layer, and interlayer dielectric ILD separates the various layers. Conductive studs called vias are made or deposited through one or more of the ILD layers to electrically connect the conductor layers. Conductive studs are called contacts when they connect the conducting lines from a lower level through dielectric called PMD to integrated semiconductor devices.
These integrated semiconductor devices include field effect transistors (FETs or MOSFETs), e.g. having a variously-doped structure including heavily-doped source and drain regions of one conductivity type (e.g., n-type in an n-FET) separated by an oppositely-doped channel region (e.g. p-type). (p-FETs have the types reversed.) The electric charge carriers for electric current in n-type material are electrons, and in p-type material they are called holes. Dopants are impurities that are intentionally originally included or subsequently introduced in the silicon or other substrate or layer, to establish the n-type or p-type conductivity. One method of such introduction is implanting, which causes energetic dopant ions to strike the surface of the substrate and create doped areas therein. The opposite-type source/channel and channel/drain regions form p-n junctions that without more would largely impede electrical conduction, but the use of a gate and introduction of voltage thereon controls electrical conduction across the channel length between the source and drain of the FET. The gate is provided as a control structure over the channel and separated from the channel by a thin gate dielectric as insulation. The gate may have a protective, insulating spacer formed laterally on either side of the gate. Application of different voltages to the gate can turn on channel conduction above a threshold voltage VT and sharply turn off channel conduction below the threshold voltage in digital switching transistors, or can intermediately vary the channel conduction in analog transistors. The ability of the FET structure to work together as a whole to effectively turn channel conduction on and off is especially important when the FET is used as a switching device, of which digital logic circuits can be composed.
CMOS (complementary metal oxide semiconductor) integrated circuit devices have both n-FETs and p-FETS. These devices are scaled or revised to make them smaller in physical dimensions of FETs and other structures at successively more advanced technology nodes. For a given fabrication process node, the node value (e.g., 28 nm) is approximately related to a smallest attainable gate length (the narrow dimension of the gate parallel to the channel length), which in turn is related to photolithography constraints at that node. (Patterned integrated circuit structures are realized by photographic exposure and chemistry-based equipments.) Small gate length or small channel length relates to desired high transistor switching speed and trades off with undesired current leakage that also increases as channel length decreases. Notice that transistors with longer gate lengths than the smallest attainable are also readily established using a given process node. Accordingly, providing transistors with such longer gate lengths in many less speed-critical circuit paths of the integrated circuit helps save power, while providing transistors with the short gate length in more speed-critical circuit paths satisfies circuit timings and delivers speed of performance.
At advanced process nodes with their smaller geometries, those processes and resulting field effect transistors (FETs) can suffer current leakage, variations in threshold voltage among seemingly similar FETs, decreased charge carrier mobility, injection of hot (higher energy) carriers from points of high electric field concentration, lowered switching threshold voltage due to short channel length and proximity of the FET drain (called drain induced barrier lowering DIBL). Shallow junctions are implanted as extensions to the more-heavily doped source and drain, to provide a decreasing doping concentration between the source/drain and the channel, which reduces electric field concentrations. These are called lightly doped drain (LDD) or medium doped drain (MDD) and prefixed with the p- or n-conductivity type of the transistor to fabricate which the LDD applies. (“LDD” is used to refer to either or both LDD and MDD herein.)
Some source/drain processing sequences are called PLDD and NLDD, which refer to p-type and n-type Lightly Doped Drain. Some LDD may execute a less-doped first implant before spacer formation, and more intensely doped implant after spacer formation. With respect to the resulting source/drain regions, the application of drain voltage causes an electric field strength or concentration that is less in the less-doped LDD drain area near the FET channel compared to the electric field that would result after applying that drain voltage to a more highly doped implant. Since the electric field is what accelerates and imparts energy to charge carriers in transistor operation, lessening the electric field strength reduces production of hot-carriers by the electric field there. (So-called hot-carriers are high-energy charge carriers that can degrade the gate oxide and reduce device reliability over time. “Hot” here does not refer to device temperature.)
Providing transistors with different gate lengths in a same process node on test chips also facilitates observation and verification of a lightly doped drain LDD process and its effect on drain induced barrier lowering DIBL and gate-to-drain capacitance Cgd. Observation of how electrical parameters vary with gate length may include studying sensitivity of DIBL to Cgd at shorter and longer gate lengths.
Source/drain extensions are areas of one or both the source and drain regions that extend toward each other and narrow the channel. As scaling proceeds to more advanced (smaller, more finely dimensioned) process technology nodes, it is becoming increasingly problematic to reduce the junction depth of source/drain extensions. This problem occurs for the nMOSFET field effect transistor at the 32 nm or 28 nm node for one instance (and can occur both at less-advanced nodes and at more-advanced nodes) due, for instance, to the lack of availability of large molecules of n-type dopants that could allow operation of ion implanters at practical implant-effective energies while providing low energy or velocity for individual dopant atoms so the implant is scaled shallower or less deep.
One might attempt to achieve shallow doping by ion implanting through a screen made up of one or more layers of deposited material to reduce the energy or velocity of incoming ions so that they are implanted into the semiconductor substrate at lower energy, and thus shallower, without having to operate the ion implanter at impractically low energies. However, after the anneal (heating step to distribute dopant) that should follow the ion implantation process, such screened dopant is prone to excessive lateral diffusion that degrades FET transistor performance. These complexities have frustrated attempts to fabricate the desired nMOSFET structure.
Such a screening approach for such LDD scaling to a more advanced process node might screen the n-type dopant during implantation in FIG. 1 to reduce the energy of the dopants entering silicon. Reduction of junction depth apparently does occur, as seen in one-dimensional (1D) SIMS data. (Secondary Ion Mass Spectrometry). SIMS sensitively detects secondary ions from a surface subjected to primary ions. In resulting semiconductor devices such screening approach has the potential to improve short channel effects SCE (such as drain induced barrier lowering DIBL and subthreshold swing). Unfortunately, such screening approach apparently also leads to excessive lateral diffusion as seen in Cgd (gate-drain capacitance) that can undesirably affect switching speed and effective gate input capacitance. As LDD junctions get shallower, e.g. with arsenic dopant, enhanced lateral diffusion apparently leads to increased gate-to-drain overlap under reported observations using SSRM (Scanning Spreading Resistance Microscopy) and SCM (Scanning Capacitance Microscopy), see Eyben, P., et al. SSRM and SCM observation of enhanced lateral As- and BF2-diffusion induced by nitride spacers. Mat. Res. Soc. Symp. Vol. 610, paper b2.2. Materials Research Society, 2000. ;see Eyben, P., et al. SSRM and SCM observation of modified lateral diffusion of As, BF2 and Sb induced by nitride spacers. Mat. Res. Soc. Symp. Vol. 669. Materials Research Society, 2001.
A form of a differential offset spacer processing has been used to increase the offset of the pMOS relative to the nMOS, because at previous nodes, scaling of the PLDD was the bigger problem. A sequence, see FIG. 1, might implant NLDD after polysilicon oxidation (polyox or Re-Ox), deposit a layer (with different spacer thickness), might do an intermediate anneal, etch, and implant PLDD—variations depending on layer material for such different spacer thickness. For some other background, see U.S. Pat. No. 7,537,988 “Differential Offset Spacer” (TI-64864) dated May 26, 2009, which is hereby incorporated herein by reference.
For still other background, see US Patent Application Publication 20080268625, Feudel et al., dated Oct. 30, 2008 and US Patent Application Publication 20100193874, Ito et al., dated Aug. 5, 2010. Compounding the problems of reliably obtaining desired transistor performances are problems posed by engineering economy because of the cost of a growing multitude of process steps.
Accordingly, significant departures and alternatives in structures, circuits, processes of manufacture, and processes of testing, for addressing the above considerations and problems would be most desirable.